Job Design Verification Engineer (System Verilog/UVM), Mississauga

Role: Design Verification Engineer (System Verilog/UVM)

Location: Markhem, ON (3 days Onsite)

Contract

Job Description:

We are seeking a motivated Design Verification Engineer with 3 years of relevant experience in System Verilog and UVM to join our dynamic team. You will play a critical role in verifying digital designs through rigorous methodologies and advanced toolsets.

Responsibilities:

• Develop testbenches and verification environments using System Verilog and UVM for IP/subsystem/SoC level testing.
• Create, enhance, and execute constrained-random and directed test cases; perform and close functional/code coverage.
• Analyze design specifications, create detailed verification plans, and validate with the engineering team.
• Debug simulation failures and collaborate closely with designers to resolve issues.
• Execute regression runs, analyze results, and contribute to continuous improvements.
• Collaborate across RTL, DFT, PD, and post-silicon teams to ensure design quality and meet project milestones.
• Document test environments, test plans, coverage reports, and provide feedback for design enhancements.

Requirements:

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field.
• Minimum 3 years hands-on experience in System Verilog and UVM.
• Proficient in building and debugging UVM/System Verilog verification environments.
• Solid understanding of AMBA or comparable interface protocols.
• Expertise in simulation and verification tools (e.g., Questa, VCS, or ModelSim).
• Excellent debugging, analytical thinking, and communication skills.
• Experience with scripting languages such as Python/TCL/Perl is an advantage.
• Familiarity with source control (Git) and Linux environments.

Nice to Have:

• Experience with power-aware simulations, low power checks, and UPF/CPF.
• Exposure to working in hybrid or international project teams.